ADVANCED IC PACKAGING: Strong momentum driven by KLA and Cadence

The semiconductor industries are competing each other to develop a new class of packages supported various next-generation and future technologies and are further accelerating packaging yield through advanced process control solutions.

Are you aware KLA recently launched advanced semiconductor packaging technique and Cadence IC Packaging Reference Flow is Certified for the Latest TSMC Advanced Packaging Solution?

let’s know more about it.

KLA launched systems for advanced semiconductor packaging techniques

With the launch of latest tools,KLA company has enhanced its systems portfolio for advanced packaging. The latest tools consist of Kronos 1190 wafer-level packaging inspection system, the ICOS F160XP and the ICOS T3/T7 Series.

The ICOS F160XP performs inspection and die sorting after wafer-level packages are tested and diced and Kronos 1190 is designed to offer inline process control for advanced wafer-level packaging steps.

Throughout the packaging assembly process,the ICOS T3/T7 Series are designed to deal with varying inspection needs.

As innovations continue to advance packaging technology, the Process control across all stages of packaging manufacturing, from wafer- to component-level process steps, becomes more crutial.

KLA newly launched products help foundries, device manufacturers and outsourced semiconductor and test (OSAT) providers meet expectations for reliability and quality in an increasingly diverse and complex packaging segment.

Cadence IC Packaging Reference Flow is now Certified

Through streamlined design, verification reference flows and analysis, multi-chip(let) advanced packages for hyperscale and networking applications can achieve increased productivity.

Cadence recently declared the certification of the Cadence tools in TSMC reference flows for TSMC’s recent Integrated Fan-Out(InFO)and (CoWoS )Chip-on-Wafer-on-Substrate advanced packaging solutions, the Integrated Fan-Out with RDL interconnect (InFO-R) and Chip-on-Wafer-on-Substrate with silicon interposer (CoWoS-S). Customers designing hyperscale and networking applications can increase productivity via streamlined design, verification reference flows and analysis,through the continued collaboration between Cadence and TSMC.

With the companies eye on performance,system-level power and area (PPA), today’s technology innovators need to create functionally dense devices with minimum power consumption and higher performance. To deliver more automation when designing advanced IC packages, Cadence and TSMC developed flows for planning, designing, analyzing and verifying each unique advanced packaging technology, delivering a clear path to meet design PPA objectives.

Cadence recent reference flows offer a more productive DRC signoff/tapeout methodology through protective and correction design automation, entitled by the Cadence Allegro package layout technology. In addition to this, customers can achieve enhanced layout automation of InFO-R packages through support for a new standard InFO techfile and design macros in the Allegro Package Designer with new in-design DRC validation and improvised performance in advanced de-gassing enabled by the Silicon Layout Option. Also,the Cadence Clarity3D Solver has been certified for 3D-EM extraction, including new support for S-parameter model creation for CoWoS-S (Chip-on-Wafer-on-Substrate with silicon interposer)designs.

Cadence tools and TSMC’s advanced packaging technology collaboration is helping their mutual customers to address design challenges for higher performance and minimum power consumption.

By continuing work with TSMC on advanced packaging technologies and techniques,Cadence has been developing tools that enable customers to achieve advanced multi-chip packaging design excellence, and , customers can attain a higher level of automation and design accuracy when targeting TSMC state-of-the-art packaging solutions. Using the recent Cadence and TSMC packaging technologies,their mutual customers can start creating designs immediately for today’s rising applications.

Want to know more about Advanced Ic packaging techniques? Here are some blogs by my teammates if you’re interested in learning more:

https://shahikirti24.medium.com/advanced-ic-packaging-requirements-challenges-and-solutions-20c9605108a6 — by Kirti Shahi

https://shraddha-kshirsagar18.medium.com/advanced-ic-packaging-1d0bac47e190 — by Shraddha Kshirsagar

https://riyakaktikar.blogspot.com/2020/12/advanced-ic-packaging-techniques_13.html — by Riya Kaktikar

https://basictermsinicpackaging.blogspot.com/ — by Ankita Karwankar

Author: RUJUTA KUMBHARE

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