The semiconductor industries are competing each other to develop a new class of packages supported various next-generation and future technologies and are further accelerating packaging yield through advanced process control solutions.

Don’t know what’s happening in the semiconductor ic packaging field?

Don’t worry, this blog will go through important highlights of 2020.let’s Know more about the recent news in the advanced ic packaging techniques.

Advanced IC packaging: OSATs, foundries, all want to be a part of business

“Today an ideal shift is going on in domain of OSATs(Outsourced Semiconductor Assembly and Test),within the packaging field of the semiconductor manufacturing supply chain, competitors from different business models, which includes foundries, substrate/PCB suppliers, are making their way in this market and cannibalizing OSATs’ share”.
Advanced packaging today , is moving from a package substrate platform to silicon, huge shift that’s providing opportunities for companies like TSMC, Samsung and Intel. These leading companies emerge as key innovators of recent advanced packaging technology and can now flex their muscles within the advanced packaging market segment.

In this highly competitive domain, TSMC especially has emerged as the leading company in terms of developing an innovative advanced packaging platform from fan-out, namely InFO(Integrated fan out), to 2.5D Si interposer, CoWoS, to 3D SoIC.
Meanwhile, other top OSATs like ASE(Advanced Semiconductor Engineering)/SPIL(Siliconware Precision Industries Co., Ltd), JCET(Jiangsu Changjiang Electronics Technology Co. Ltd.) and Amkor are investing in various advanced ic packaging techniques like SiP and fan-out technologies to extend their competition and their share of the advanced packaging market. PCB manufacturers, IC substrate &EMS companies, and display industry players also are entering the advanced packaging arena via panel-level fan-out packages, SiPs, and embedded dies (and passives) in organic substrates. This trend will continue in 2020 and beyond.

  • In 2019,Advanced packaging was a US$29 billion market. It’s expected to grow at 6.6% CAGR between 2020 and 2025.
  • Due to Moore’s Law and heterogeneous integration, together with the megatrends 5G,HPC , IoTs , AI , etc, the share of the advanced ic packaging market segment within the full semiconductor manufacturing market is continuously increasing.
    It will reach almost 50% of the overall market by 2025.
  • Technology status:
    Advanced Ic packaging techniques are now moving from package substrates to silicon platforms. This trend is offering huge opportunities for Intel,TSMC and Samsung.
  • Competitive landscape:
    Advanced packaging at TSMC has become a fully developed business in itself.
    With an expected US$2,8 billion revenue from advanced packaging activities in 2019, TSMC achieved 4th position in the 2019 OSATs ranking.
  • COVID-19 impact:
    In 2020, Looking towards the market side the advanced packaging market is decreased by 7 percent, while the traditional packaging market is decreased by 15 percent.

Do you know Systems and appliances in several domains such as transportation systems, industrial, home appliances, medical, information including others, comprise of semiconductor chips? The process of semiconductor ic packaging is one of the most productive sectors. Have a look at the recent news in advanced ic packaging market.

Advanced Packaging Market 8% growth in 2020–2026

As per the recent study from market research firm Global Market Insights, the advanced packaging market will grow from its current market value of more than $25 billion to over $40 billion by 2026, gaining remarkable growth over the 2020 to 2026 period.

The advanced packaging market is ready to accumulate notable profits in the coming years due to the adoption of high-quality products in applications such as health care, automotive, consumer electronics, aerospace, and defense. Advanced packaging enhances the performance of the device and simultaneously shrinks the packages. In short it is general grouping of a mixture of different techniques, such as system-in-package, 3D-IC, 2.5D, and fan-out wafer-level (FOWL)packaging.

Semiconductor packaging materials are well-known to be a group of electronic solutions utilized to form the connection of the IC chip to the packaging substrate.

The advanced packaging market divide in terms of packaging type, application, and regional landscape. For packaging type, the advanced packaging market is grouped into 5 categories, which are 2.5D/3D, fan-out, embedded-die, fan-in WLP, including flip-chip. Among these five categories , the fan-in WLP technique will see considerable growth over the coming years.

The development is attributed to the growing adoption of AI chipsets across healthcare applications, mainly for remote monitoring, which is further likely to increase the demand for advanced packaging. Also, the increasing need for advanced packaging for miniaturized devices is urging the product request across healthcare applications.

Have you heard about advanced ic packaging capabilities of companies such as samsung, amkor ? let’s get an idea about this recent news.

Samsung’s Advanced IC Packaging Capabilities

The feature-size shrinking is getting more complex and costly. In Advanced IC packaging, multi-die packaging is, in most cases, a better way of packing more functionality into an IC package and with it, continues growing chances for industry. The requirement for much higher bandwidth than single-die ICs on a printed circuit board can offer as a key reason for multi-die packaging.

Samsung’s hybrid bonding technology and its integrated stack capacitor (ISC), decreases mid/high-frequency noise. As the complexity of multi-die IC packaging solutions is increasing , challenges such as IR drop, supply noise, crosstalk, signal degradation, thermal-mechanical interactions, and other factors in a die-package-board assembly, need to be inspected.

Amkor’s Advanced IC Packaging Capabilities

There are various demands and trends in the mobility market, in the Internet of things (IoT)/consumer applications, automotive, and high-performance computing (HPC) and networking systems. Let’s take an example, mobility devices demand 5G and a tiny form factor. IoT edge nodes require high levels of heterogeneous integration and ultra-low power designs and for automotive, reliability is the main criterion. Data Centers require performance, very high levels of integration, and heat management. These significantly different requirements, and frequent needs for customization of packaging solutions, the importance of having clear hand-off criteria between customer and assembly partner and demand an excellent working relationship for successful cooperation.

The other major packaging demands — like form factor reduction, high-power management, electrical-thermal-mechanical interactions — that challenge IC assembly houses and their suppliers.

The future of packaging will mean resolving those challenges by meeting innovation milestones including:

  • Complex modular systems for miniaturization
  • Electrical microsystems targeted to IoT, 5G and AI
  • Electrically and mechanically advanced materials
  • Power dissipation to handle higher power density

Another significant packaging trend: Customers want chiplets (a.k.a. bare dice, semiconductor IP building blocks in die-form), to reach far beyond the complexity limits of single-die SoCs, cut time to market, keep design risk manageable, and, most importantly, lower development and unit cost. Chiplets allow the integration of heterogeneous functions (logic, memories, analog, MEMS(Micro-electromechanical systems), etc.), each function assembled in the most appropriate and cost-effective process technology.

Amkor is also advancing hybrid bonding techniques that will permit sub-micron pads and pitches in the future.

IC packaging experts have to serve various applications. To do this, Amkor has developed a broad range of packaging technologies — e.g. FC-MCM(Flip Chip MultiChip Module on Laminate), 2.5D & TSV(Through-silicon via), SWIFT-Silicon Wafer Integrated Fan-out Technology, & HDFO -High density Fan-out.


With its efforts to extend the validity of Moore’s Law, TSMC has been dedicating a lot of efforts to developing packaging technology. The foundry house’s packaging technology development is expected to remain focused on SoIC and organic interposer in 2021. Its major foundry rival, Samsung, is also stepping up development of packaging technology. For Intel, Moore’s Law remains an encouragement for its chip development, according to the company’s chief architect Raja Koduri.

TSMC packaging development to remain concentrated on SoIC ,organic interposer in 2021:TSMC is awaited to continue its advanced packaging development focus on 3D SoIC (system on integrated chips) technology and organic interposer in 2021, while it has fabricated WSE (wafer-scale engine) AI chips for Cerebras with InFo-SoW(Integrated Fan-Out Silicon on Wafer) packaging process and second-generation 7nm node, as per the industry sources.

Samsung stepping up efforts for advanced chip packaging :Samsung is stepping up its deployments in the 3D IC packaging field, looking to compete against TSMC starting 2022 for advanced chip packaging in-house, according to industry observers.


Want to know more about Advanced Ic packaging techniques? Here are some blogs by my teammates if you’re interested in learning more: — by Kirti Shahi — by Shraddha Kshirsagar by Riya Kaktikar Ankita Karwankar


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To the readers, do read my other blog on ADVANCED IC PACKAGING: Strong momentum driven by KLA and Cadence. Find the mentioned link.

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